module bcd_counter_60(Clk_50M, Rst_n, Bcd_out);
	
	input Clk_50M;
	input Rst_n;
	output reg[5:0] Bcd_out;
	
	always @(posedge Clk_50M or negedge Rst_n) begin
		
		if(Rst_n == 1'b0) begin
			Bcd_out <= 6'b00_0000;
		end
		else if(Bcd_out === 6'b11_1011) begin
			Bcd_out <= 6'b00_0000;
		end
		else begin
			Bcd_out <= Bcd_out + 1;
		end
	
	end
	
endmodule
